Dynamic random access memory (DRAM) is a general purpose high-performance memory device suitable for use in a broad range of applications. DRAM allows high bandwidth for multiple, simultaneous, randomly addressed memory transactions.
DRAM also may include a nap/powerdown state. The powerdown state is the lowest power state available. In these states the information in the DRAM core is maintained with self-refresh, using an internal timer. The powerdown (PDN) state has a relatively long exit latency because of clock resynchronization. An internal clock in the memory is turned off during the PDN state and needs to be resynchronized to an external clock in order to permit normal memory access.
The Nap state is another low-power state in which either self-refresh or REFA refresh are used to maintain the information in the DRAM core. Self-refresh uses an internal timer to refresh the memory. The Nap state has a shorter exit latency because the internal clocks in the memory system are maintained synchronized relative to the external clock signal.
FIG. 1 illustrates a state diagram of a prior art memory. State 110 is the nap/powerdown state. The states used to enter into the nap/powerdown state are not illustrated in this figure. The memory may remain in the nap/powerdown state 110 for a period of time. A signal 120 sent by the CPU is received by the memory controller to initiate exit from the nap/powerdown state, moving the memory to the wait for nap exit delay state 130. The memory is awakened, clocks are resynchronized, and other "clean-up" steps are taken at this point. The time used for these steps is the "nap exit delay" or "powerdown exit delay."
After the nap exit delay, the system receives simultaneous quiet times on the row and column-access control signal pins of the memory. This moves the memory to the Looking for packet frame state 140.
FIG. 2 illustrates a timing diagram of the prior art system. The CTM/CFM signals 270 are clock to master and clock from master, respectively. The CTM/CFM signals 270 are used by the memory to time data to and from the memory controller. The row-access control signals 210 and column-access control signals 220 carry data that identifies the memory location for memory access. The DQA0 . . . 8 and DQA0 . . . 8 signals 230 are data signals on a data transfer bus.
The SCK signal 240 is a clock signal is used to time the exit from the nap/powerdown mode. The CMD signal 250 is a command signal used to initialize the exit from the nap/powerdown state. The CMD signal 250 is sampled on both clock edges, the rising edge and the falling edge. To signal the exit from the powerdown mode, the CMD signal 250 transitions from a zero on a first falling clock edge to a one on the next rising clock edge. On a falling and rising edge of SCK signal 240, if there is a "01" on the CMD input, NAP or PDN state will be exited. On a falling edge of the SCK signal 240, the SIOin signal 260 indicates whether the exit is from a NAP state or a PDN state.
In powerdown mode, the CTM/CFM clocks 270 are stopped and must be restarted and stabilized for time t.sub.CE before a powerdown exit command can be sent. In nap mode, the CTM/CFM clocks 270 are running, and the nap exit command can be sent whenever needed. In both cases, the dynamic locked loops (DLLs) in the DRAMs must be restarted and the internal timing circuits of the memory must be resynchronized. After the CTM/CFM clocks 270 become stable, a 0 or 1 is sent on the CMD input on the next falling edge of the SCK signal 240, for nap and powerdown exit respectively.
On the next rising edge of the SCK signal 240, a signal identifying the device, PDEV 280, is sent on the DQx pins. The PDEV signal 280 identifies the memory devices that are being woken up.
A time t.sub.NXB or t.sub.PXB --referring either to nap exit delay or powerdown exit delay--after the falling edge of the SCK signal 240, the row and column-access control signals 210, 220 must be quiet. The quiet time 290 on the row and column-access control signals 210, 220 must occur exactly t.sub.NXB or t.sub.PXB after the appropriate falling edge of the SCK signal 240. During the quiet time, which lasts at least eight clock edges of the CTM/CFM signals 270, or at least two clock edges of the SCK signal 240, no commands may be on the column or row-access control signals 210, 220.
Timing a quiet time requires complex processing. If there are commands on the column 220 or row-access control pins 230 at the time the quiet time needs to occur, the memory may be corrupted. Therefore, a worst case scenario must be taken into consideration when designing the memory controller. In the prior art, the memory itself is not aware of the quiet time scheduling and expects a quiet time 290 at an exact time after the t.sub.NXB or t.sub.PXB.
DRAMs are often used in highly pipelined systems. Pipelined systems generally send interrelated and interwoven commands to memory. In order to process a quiet signal 290 at the appropriate time, the commands that would normally be sent during that period must be rescheduled or held for later processing (stalled). All of the commands that are related to the rescheduled commands must be considered. For example, a row signal 210 may be sent on the row pins. A column signal 220 must be sent a set period after the row signal. This may disrupt pipelining and result in incomplete commands that may result in false data.
One prior art solution is to insert a buffer time prior to the expiration of the nap/powerdown delay. For a time t.sub.buff prior to the expiration of the delay t.sub.NXB or t.sub.PXB no new instructions are sent on the pipeline. The time t.sub.buff is set such that prior to the expiration of the delay t.sub.NXB or t.sub.PXB, all instructions and data that follow the last pipelined instruction can be completed. Thus, for example, t.sub.buff is sufficiently long to permit a response for a read query from memory. However, t.sub.buff inserts a delay into the pipeline and slows down instruction processing.
In the prior art, the quiet time is timed at exactly the same time on the row and column-access control signal pins 210, 220. Because the DRAM may address the row 220 and column-access control signal pins 210 separately, both must be made inactive separately. This requires more processing in the memory controller. Additionally, because of the cushioning of related commands around the quiet time 290, it may induce a longer delay in the signals being sent to the memory.
Therefore, a better method of exiting a memory from a low power state would be advantageous.